The present invention relates to integrated circuits, semiconductor chips and the like, and more particularly to a to a system and method to test an integrated circuit, semiconductor chip on a wafer.
Testing integrated circuits, semiconductor chips and the like at various stages of the manufacturing process can be advantageous as processing adjustments may be made or other remedial operations may be performed to realize higher yields. Capturing information regarding fluctuations and failures during the manufacturing process can have a substantial impact on the overall product cost. For some emerging forms of regular logic, back-end-of-line (BEOL) processing adjustments and changes could be made to permit substantially complete utilization of what would otherwise be partially non-functioning silicon. However, testing chips during the manufacturing process and while the chips are still part of a wafer, presents many challenges.
One means of testing chips during various stages of the manufacturing process is wafer probe testing. However, such testing is not without its limitations. Wafer probe testing is costly and limited in terms of the extent to which it may be used. During early stages of in-line manufacturing testing, the wafers must be maintained in their manufacturing environment. Additionally, wafer probe testing of all chips and collecting test data from all chips in the manufacturing environment is impractical. For end-of-line testing, the environmental issues are less of a problem, but the process is still costly. During wafer sort, probe testing is still time consuming and therefore costly and issues exist with respect to contact resistance associated with the probes which can impact overall yield.